Search - RAM vhdl

[VHDL-FPGA-Verilog] ref-sdr-sdram-vhdl

Description: 基于VHDL编写的SDR-SDRAM控制器的编程，目前是业界常用的RAM控制器-VHDL prepared based on the SDR-SDRAM controller programming, is now commonly used in industry RAM controller
Platform: | Size: 1013760 | Author: wfs | Hits:

[Software Engineering] 20060510191318991

Description: ALTERA公司DDR ram controller资料-ALTERA company DDR ram controller information
Platform: | Size: 2253824 | Author: 盛雪飞 | Hits:

[VHDL-FPGA-Verilog] ram

Description: 存储器模块生成，采用16位数据总线，5位读写地址总线，异步清零！-Memory modules generated, using 16-bit data bus, 5 to read and write address bus, asynchronous Clear!
Platform: | Size: 2048 | Author: 齐磊 | Hits:

[VHDL-FPGA-Verilog] VHDL

Description: 采用VHDL语言设计一个4通道的数据采集控制模块。系统的功能描述如下： 1.系统主时钟为100 MHz。 2.数据为16位-数据线上连续2次00FF后数据传输开始。 3.系统内部总线宽度为8位。 4.共有4个通道（ch1、ch2、ch3、ch4），每个通道配备100 Bytes的RAM，当存满数据后停止数据采集并且相应通道的状态位产生报警信号。 5.数据分为8位串行输出，输出时钟由外部数据读取电路给出。 6.具备显示模块驱动功能。由SEL信号设置显示的通道，DISPLAY信号启动所选通道RAM中数值的显示过程。数值顺次显示一遍后显示结束，可以重新设定SEL的值选择下一个通道。模块数据线为8位，显示器件为4个8段LED。 7.数据采集模式如下：单通道采集（由SEL信号选择通道），多通道顺次采集（当前通道采满后转入下一通道），多通道并行采集（每通道依次采集一个数据）。模式由控制信号MODE选择，采集数据的总个数由NUM_COLLECT给出。 8.数据采集过程中不能读取，数据读取过程中不能采集-err
Platform: | Size: 5782528 | Author: pengfu | Hits:

[DSP program] 2812RAM

Description: TMS320F2812读写外部RAM的C语言例程，TMS320F2812读写外部RAM的C语言例程-TMS320F2812 external RAM read and write the C language routines, TMS320F2812 external RAM read and write the C language routines
Platform: | Size: 36864 | Author: 王磊 | Hits:

[Software Engineering] TopLevel_DualPort_Ram_XilinxCore

Description: Top Level Dual Port Ram Core Project, VHDL code
Platform: | Size: 1024 | Author: mohd | Hits:

[VHDL-FPGA-Verilog] connect20090223

Description: fpga从FIFO读数据并上传到双口ram中。-FPGA read data from the FIFO and upload it to dual-port ram Medium.
Platform: | Size: 468992 | Author: 张菁 | Hits:

[VHDL-FPGA-Verilog] pingpangVHDL

Description: 据说是 vhdl的乒乓ram 代码提供给大家做个参考吧 -It is said VHDL code of the ping-pong ram available to the U.S. to be a reference to it
Platform: | Size: 1024 | Author: 白饭 | Hits:

[VHDL-FPGA-Verilog] dual_port_ram

Description: 实现双口ram的读写功能，并含有测试文件，已经经过方针验证，很好用的-the writing and reading to the dual port ram ,good
Platform: | Size: 274432 | Author: zhangyan | Hits:

[VHDL-FPGA-Verilog] XAPP204

Description: Using Block RAM for High-Performance Read.Write Cams
Platform: | Size: 55296 | Author: ryan | Hits:

[Linux-Unix] DP_RAM_lab

Description: 用SmartGen 生成一个2k*8 Dual Port RAM，并通过串口发送数据初始化RAM。然后通过串口返回到上位机的串口调试程序显示。-SmartGen generated using a 2k* 8 Dual Port RAM, and sending data through the serial port to initialize RAM. And back through the serial port to the PC serial port debugger display.
Platform: | Size: 4096 | Author: 劳杰勇 | Hits:

[Other] FIFORAM

Description: FIFO RAM 存储器以FIFO形式进行的读取-FIFO RAM
Platform: | Size: 331776 | Author: SMILE | Hits:

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[VHDL-FPGA-Verilog] ref-sdr-sdram-vhdl

[Software Engineering] 20060510191318991

[VHDL-FPGA-Verilog] ram

[VHDL-FPGA-Verilog] VHDL

[DSP program] 2812RAM

[Software Engineering] TopLevel_DualPort_Ram_XilinxCore

[VHDL-FPGA-Verilog] connect20090223

[VHDL-FPGA-Verilog] pingpangVHDL

[VHDL-FPGA-Verilog] dual_port_ram

[VHDL-FPGA-Verilog] XAPP204

[Linux-Unix] DP_RAM_lab

[VHDL-FPGA-Verilog] ram_Test

[VHDL-FPGA-Verilog] the_VHDL_programe_of_generate_RAM

[VHDL-FPGA-Verilog] 75_RAM

[VHDL-FPGA-Verilog] ram

[VHDL-FPGA-Verilog] DDR_SDRAM

[VHDL-FPGA-Verilog] ram32b

[VHDL-FPGA-Verilog] RAM_Examples

[VHDL-FPGA-Verilog] Ram_interface

[Other] FIFORAM

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